Soi lateral bipolar junction transistor having a wide band gap emitter contact

ABSTRACT

A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.

BACKGROUND

The present disclosure relates to a lateral bipolar transistor (BJT)structure, and particularly to a lateral bipolar junction transistorincluding a wide band gap emitter contact and methods of manufacturingthe same.

Heterojunction bipolar junction transistors (HBTs) known in the artinclude a heterojunction, i.e., a junction of two semiconductormaterials having different band gaps, that coincide with a p-n junctionbetween the base and the emitter. The heterojunction at which twodifferent semiconductor materials having different band gaps are joinedcoincide with the p-n junction. The wider band gap of the emitterrelative to the band gap of the base in an HBT increases the currentgain relative to a bipolar junction transistor employing a samesemiconductor material across the base and the emitter and havingsimilar physical dimensions and doping profiles for the base andemitter.

While the increase in the current gain obtained by an HBT is desirable,the heterojunction between two semiconductor materials having differentband gaps results in a lattice mismatch at the heterojunction.Dislocations are formed in the vicinity of the heterojunction to relievethe stress generated by the lattice mismatch. However, the dislocationsin the vicinity of the p-n junction function as scattering centers forcharge carriers, reducing the current flow between the emitter and thebase. The dislocations may also act as generation and recombinationcenters, causing an undesirable increase in p-n junction leakagecurrent. Thus, HBTs known in the art suffer from the deleterious effectof the dislocation centers around the p-n junction despite theadvantageous effect of providing a relatively high current gain throughformation of the heterojunction between the emitter and the base.

BRIEF SUMMARY

A lateral heterojunction bipolar transistor (HBT) is formed on asemiconductor-on-insulator substrate including a top semiconductorportion of a first semiconductor material having a first band gap and adoping of a first conductivity type. A stack of an extrinsic base and abase cap is formed such that the stack straddles over the topsemiconductor portion. A dielectric spacer is formed around the stack.Ion implantation of dopants of a second conductivity type is performedto dope regions of the top semiconductor portion that are not masked bythe stack and the dielectric spacer, thereby forming an emitter regionand a collector region. The region of the top semiconductor portionbetween the emitter region and the collector region constitutes a baseregion. A second semiconductor material having a second band gap greaterthan the first band gap and having a doping of the second conductivitytype is selectively deposited on the emitter region and the collectorregion to form an emitter contact region and a collector contact region,respectively. The heterojunction between the emitter region and theemitter contact region increases the current gain relative to bipolartransistors without a heterojunction, while dislocations are minimizedaround the p-n junction between the emitter region and the base region.

According to an aspect of the present disclosure, a semiconductorstructure including a bipolar junction transistor (BJT) is provided. TheBJT includes: a base region including a first portion of a firstsemiconductor material having a first band gap and having a doping of afirst conductivity type; an emitter region including a second portion ofthe first semiconductor material, having a doping of a secondconductivity type that is the opposite of the first conductivity type,and laterally contacting the base region; and an emitter contact regionincluding a portion of a second semiconductor material having a secondband gap that is greater than said first band gap, having a doping ofthe second conductivity type, and contacting the emitter region.

According to another aspect of the present disclosure, a method offorming a semiconductor structure including a bipolar junctiontransistor (BJT) is provided. The method includes: providing a substrateincluding a semiconductor portion including a first semiconductormaterial having a first band gap and having a doping of a firstconductivity type; converting a region of the semiconductor portion intoan emitter region by introducing dopants of a second conductivity typethat is the opposite of the first conductivity type into the region ofthe semiconductor portion, wherein a remaining region of thesemiconductor portion constitutes a base region that laterally contactsthe emitter region; and depositing an emitter contact region including aportion of a second semiconductor material having a second band gap thatis greater than the first band gap and having a doping of the secondconductivity type directly on the emitter region.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a vertical cross-sectional view of an exemplary semiconductorstructure after providing a semiconductor-on-insulator (SOI) substrateaccording to an embodiment of the present disclosure.

FIG. 2 is a vertical cross-sectional view of the exemplary semiconductorstructure after deposition of an extrinsic base layer and a base caplayer according to an embodiment of the present disclosure.

FIG. 3 is a vertical cross-sectional view of the exemplary semiconductorstructure after patterning of the base cap layer and the extrinsic baselayer according to an embodiment of the present disclosure.

FIG. 4 is a vertical cross-sectional view of the exemplary semiconductorstructure after formation of a dielectric spacer according to anembodiment of the present disclosure.

FIG. 5 is a vertical cross-sectional view of the exemplary semiconductorstructure after selective deposition of an emitter contact region and acollector contact region according to an embodiment of the presentdisclosure.

FIG. 6 is a vertical cross-sectional view of the exemplary semiconductorstructure after formation of metal semiconductor alloy regions accordingto an embodiment of the present disclosure.

FIG. 7 is a vertical cross-sectional view of the exemplary semiconductorstructure after formation of a contact-level dielectric layer andcontact via structures according to an embodiment of the presentdisclosure.

FIG. 8 is a band diagram of an NPN transistor according to an embodimentof the present disclosure.

FIG. 9 is a band diagram of a PNP transistor according to an embodimentof the present disclosure.

FIG. 10 is a vertical cross-sectional view of a variation of theexemplary semiconductor structure at a processing step corresponding toFIG. 3.

FIG. 11 is a vertical cross-sectional view of the variation of theexemplary semiconductor structure at a processing step corresponding toFIG. 7.

DETAILED DESCRIPTION

As stated above, the present disclosure relates to a lateral bipolarjunction transistor including a wide band gap emitter contact andmethods of manufacturing the same, which are now described in detailwith accompanying figures. It is noted that like and correspondingelements mentioned herein and illustrated in the drawings are referredto by like reference numerals.

Referring to FIG. 1, an exemplary semiconductor structure according toan embodiment of the present disclosure includes a substrate 8. Thesubstrate 8 as provided includes at least a stack of a semiconductorlayer and an insulator layer. For example, the substrate 8 can be asemiconductor-on-insulator (SOI) substrate including a stack, frombottom to top, a handle substrate 10, a buried insulator layer 20contacting a top surface of the handle substrate 10, and a topsemiconductor layer 30L contacting the top surface of the buriedinsulator layer 20. The top semiconductor layer 30L as provided caninclude a semiconductor material that extends across the entirety of theburied insulator layer 20.

The handle substrate 10 can include a semiconductor material, aninsulator material, a conductor material, or a combination thereof. Inone example, the handle substrate 10 can include a semiconductormaterial such as silicon. If the handle substrate 10 includes asemiconductor material, the handle substrate 10 can be undoped or have ap-type doping or an n-type doping.

The buried insulator layer 20 includes a dielectric material such assilicon oxide and/or silicon nitride. For example, the buried insulatorlayer 20 can include thermal silicon oxide. The thickness of the buriedinsulator layer 20 can be from 5 nm to 1000 nm, and typically from 100nm to 200 nm, although lesser and greater thicknesses can also beemployed. The buried insulator layer 20 may, or may not, includemultiple dielectric layers, e.g., a stack including at least a siliconoxide layer and a silicon nitride layer.

The top semiconductor layer 30L as provided in the SOI substrate can bea planar semiconductor material layer 30 having a thickness from 5 nm to1,000 nm. The semiconductor material in the planar semiconductormaterial layer 30 is herein referred to as a first semiconductormaterial. The first semiconductor material has a first band gap and hasa doping of a first conductivity type. The first semiconductor materialcan be any semiconductor material known in the art provided that anothersemiconductor material having a greater band gap than the firstsemiconductor material exists. The first semiconductor material can beselected from Group IV elemental semiconductors, Group IV compoundsemiconductors, III-V semiconductors, II-VI semiconductors, I-VIIsemiconductors, IV-VI semiconductors, IV-VI semiconductors, V-VIsemiconductors, II-V semiconductors, semiconducting oxides, layeredsemiconductors, magnetic semiconductors, organic semiconductors,semiconducting charge-transfer complexes, semiconducting alloys thereof,or a combination thereof. The first semiconductor material can be, forexample, crystalline carbon, silicon, germanium, a silicon germaniumalloy, silicon carbide, aluminium antimonide, aluminium arsenide,aluminium nitride, aluminium phosphide, boron nitride, boron phosphide,boron arsenide, gallium antimonide, gallium arsenide, gallium nitride,gallium phosphide, indium antimonide, indium arsenide, indium nitride,indium phosphide, aluminium gallium arsenide, indium gallium arsenide,indium gallium phosphide, aluminium indium arsenide, aluminium indiumantimonide, gallium arsenide nitride, gallium arsenide phosphide,gallium arsenide antimonide, aluminium gallium nitride, aluminiumgallium phosphide, indium gallium nitride, indium arsenide antimonide,indium gallium antimonide, aluminium gallium indium phosphide, aluminiumgallium arsenide phosphide, indium gallium arsenide phosphide, indiumgallium arsenide antimonide, indium arsenide antimonide phosphide,aluminium indium arsenide phosphide, aluminium gallium arsenide nitride,indium gallium arsenide nitride, indium aluminium arsenide nitride,gallium arsenide antimonide nitride, gallium indium nitride arsenideantimonide, gallium indium arsenide antimonide phosphide, cadmiumselenide, cadmium sulfide, cadmium telluride, zinc oxide, zinc selenide,zinc sulfide, zinc telluride, cadmium zinc telluride, mercury cadmiumtelluride, mercury zinc telluride, mercury zinc selenide, cuprouschloride, copper sulfide, lead selenide, lead telluride, tin sulfide,tin telluride, lead tin telluride, thallium tin telluride, thalliumgermanium telluride, bismuth telluride, cadmium phosphide, cadmiumarsenide, cadmium antimonide, zinc phosphide, zinc arsenide, zincantimonide, titanium dioxide, copper oxide, uranium dioxide, uraniumtrioxide, bismuth trioxide, tin dioxide, barium titanate, strontiumtitanate, lithium niobate, lanthanum copper oxide, lead iodide,molybdenum disulfide, gallium selenide, tin sulfide, bismuth sulfide,gallium manganese arsenide, indium manganese arsenide, cadmium manganesetelluride, lead manganese telluride, lanthanum calcium manganate, ironoxide, nickel oxide, europium oxide, europium sulfide, chromium bromide,copper indium gallium selenide, copper zinc tin sulfide, copper indiumselenide, silver gallium sulfide, zinc silicon phosphide, arsenicselenide, platinum silicide, bismuth iodide, mercury iodide, thalliumbromide, selenium, silver sulfide, an alloy thereof, or a stack thereof,provided that another semiconductor material having a greater band gapthan the selected first semiconductor material exists.

In one embodiment, the first semiconductor material can be a singlecrystalline semiconductor material. In another embodiment, the firstsemiconductor material can be germanium or a silicon germanium alloy. Inyet another embodiment, the first semiconductor material can be singlecrystalline germanium or a single crystalline silicon germanium alloy.In still another embodiment, the first semiconductor material can be apolycrystalline material or an amorphous material.

The first semiconductor material has a doping of a first conductivitytype, i.e., doped with electrical dopants of the first conductivitytype. The first conductivity type can be p-type or n-type. If the firstconductivity type is p-type, the electrical dopants can be, for example,B, Al, Ga, In, and/or Tl. If the first conductivity type is n-type, theelectrical dopants can be, for example, P, As, and/or Sb. The dopantconcentration in the first semiconductor material can be from1.0×10¹⁵/cm³ to 3.0×10¹⁹/cm³, although lesser and greater dopantconcentrations can also be employed.

Referring to FIG. 2, at least one shallow trench extending at least tothe top surface of the buried insulator layer 20 is formed through theplanar semiconductor material layer 30, and is subsequently filled witha dielectric material such as silicon oxide, silicon nitride, and/orsilicon oxynitride. The at least one shallow trench can be formed tolaterally enclose an unetched region of the planar semiconductormaterial layer 30, which is herein referred to as a top semiconductorportion 31. Thus, the top semiconductor portion 31 is formed bypatterning the top semiconductor layer 30L as provided with a shallowtrench that extends at least to the top surface of the buried insulatorlayer 20. A remaining portion of the top semiconductor layer 30L is thetop semiconductor portion 31.

The top semiconductor portion 31 is a semiconductor portion that ispresent within the top semiconductor layer 30L. Excess portions of thedielectric material is removed from above the top surface of the topsemiconductor portion 31, for example, by a recess etch or chemicalmechanical planarization (CMP). A remaining portion of the dielectricmaterial that fills the at least one shallow trench constitutes at leastone shallow trench isolation structure 22. One of the at least oneshallow trench isolation structure laterally encloses, and contacts allsidewalls of, the top semiconductor portion 31 illustrated in FIG. 2.The top surface(s) of the at least one shallow trench isolationstructure 22 can be substantially coplanar with, raised above, orrecessed below, the top surface of the top semiconductor portion 31. Asused herein, a first surface is “substantially coplanar” with a secondsurface if the offset between the first surface and the second surfaceis does not exceed inherent height variations in the first surface orthe second surface that are introduced during currently availablemanufacturing processes.

An extrinsic base layer 52L and a base cap layer 59L are sequentiallydeposited over the top semiconductor layer 30L. The extrinsic base layer52L can be a doped semiconductor material layer having a doping of thefirst conductivity type. The doped semiconductor material of theextrinsic base layer 52L is herein referred to as an extrinsic basesemiconductor material. In one embodiment, the extrinsic base layer 52Lincludes a different semiconductor material than the top semiconductorportion 31. In another embodiment, the extrinsic base layer 52L includesa same semiconductor material as the top semiconductor portion 31. Inone embodiment, the extrinsic base layer 52L can be polycrystalline oramorphous as deposited. In another embodiment, the top semiconductorportion 31 can be single crystalline, and the extrinsic base layer 52Lcan be epitaxially aligned to the top semiconductor portion 31, andcorrespondingly, single crystalline.

The extrinsic base layer 52L has a doping of the first conductivitytype. The extrinsic base layer 52L can be in-situ doped duringdeposition, or can be deposited as an intrinsic semiconductor materiallayer and subsequently doped by ion implantation, gas phase doping,plasma doping, or diffusion of electrical dopants from a disposabledopant source layer (such as a phosphosilicate glass layer, aborosilicate glass layer, or an arsenosilicate glass layer). In oneembodiment, the extrinsic base layer 52L includes dopants of the firstconductivity type at a greater dopant concentration than theconcentration of dopants of the first conductivity type within the topsemiconductor portion 31. For example, the extrinsic base layer 52Lincludes dopants of the first conductivity type at a dopantconcentration from 1.0×10¹⁸/cm³ to 3.0×10²¹/cm³, although lesser andgreater dopant concentrations can also be employed. In one embodiment,the extrinsic base layer 52L can include a doped polycrystallinematerial having a doping of the first conductivity type. The extrinsicbase layer 52L can be deposited, for example, by chemical vapordeposition (CVD) or physical vapor deposition (PVD). The thickness ofthe extrinsic base layer 52L can be from 10 nm to 1,000 nm, althoughlesser and greater thicknesses can also be employed.

The base cap layer 59L includes a dielectric material such as siliconoxide, silicon nitride, silicon oxynitride, a dielectric metal oxide, ora combination thereof. The base cap layer 59L can be deposited, forexample, by chemical vapor deposition (CVD). The thickness of the basecap layer 59L can be from 10 nm to 1,000 nm, although lesser and greaterthicknesses can also be employed. In one embodiment, the thickness ofthe base cap layer 59L can be selected to have the same stopping poweras, or a greater stopping power than, the top semiconductor portion 31for ion implantation, to be subsequently performed, of dopants of asecond conductivity type that is the opposite of the first conductivitytype. In one embodiment, a dielectric material different from thedielectric materials of the at least one shallow trench isolationstructure 22 is employed for the base cap layer 59 so that the materialof the base cap layer 59L can be subsequently removed selective to thematerial of the at least one shallow trench isolation structure 22.

Referring to FIG. 3, the stack of the base cap layer 59L and theextrinsic base layer 52L is patterned, for example, by applying andlithographically patterning a photoresist layer 57 and transferring thepattern in the patterned photoresist layer 57 through the stack of thebase cap layer 59L and the extrinsic base layer 52L. A remaining portionof the base cap layer 59L is herein referred to as a base cap 59, and aremaining portion of the extrinsic base layer 52L is herein referred toas an extrinsic base region 52. The transfer of the pattern from thepatterned photoresist layer 57 to the stack of the base cap layer 59Land the extrinsic base layer 52L can be effected by an anisotropic etch,in which case the sidewalls of the extrinsic base region 52 isvertically coincident (coincident in a top-down view) with sidewalls ofthe base cap 59.

The horizontal cross-sectional shape of the base cap 59 and theextrinsic base region 52 is selected such that the stack of theextrinsic base region 52 and the base cap 59 straddles over a middleportion of the top semiconductor portion 31. The stack of the extrinsicbase region 52 and the base cap 59 can extend across the topsemiconductor portion 31 and two end portions of the stack of theextrinsic base region 52 and the base cap 59 can overlie the at leastone shallow trench isolation structure 22. Thus, the top surface of afirst peripheral portion of the top semiconductor portion 31 isphysically exposed on one side of the stack of the extrinsic base region52 and the base cap 59, and the top surface of a second peripheralportion of the top semiconductor portion 31 is physically exposed onanother side of the stack of the extrinsic base region 52 and the basecap 59 after formation of the stack of the extrinsic base region 52 andthe base cap 59.

The endpointing of the anisotropic etch that forms the stack of theextrinsic base region 52 and the base cap 59 can be effected bydetecting physical exposure of the top surface of the at least oneshallow trench isolation structure 22 through optical means or throughdetection of change of radical composition in the plasma of theanisotropic etch. Alternately or additionally, if the firstsemiconductor material is different from the extrinsic basesemiconductor material, the endpointing of the anisotropic etch can beeffected by detecting physical exposure of the top surface of the topsemiconductor portion 31 through optical means or through detection ofchange of radical composition in the plasma of the anisotropic etch. Yetalternately or additionally, if there exists an interfacial layer suchas a native oxide layer (having a thickness on the order of one atomiclayer of a semiconductor oxide) at the interface between the topsemiconductor portion 31 and the extrinsic base layer 52, an etchchemistry that is highly selective to a semiconductor oxide can beemployed to minimize an overetch into the top semiconductor portion 31.

In one embodiment, physically exposed surfaces of the top semiconductorportion 31 after the anisotropic etch can be substantially coplanar withthe interface between the top semiconductor portion 31 and the extrinsicbase region 52. In another embodiment, physically exposed surfaces ofthe top semiconductor portion 31 after the anisotropic etch can berecessed relative to the interface between the top semiconductor portion31 and the extrinsic base region 52. While the present disclosure isdescribed employing an anisotropic etch, an embodiment in which anisotropic etch such as a wet etch is employed to transfer the pattern inthe patterned photoresist layer 57 through the stack of the extrinsicbase region 52 and the base cap 59 is also contemplated. Use of anisotropic etch may be suitable if the lateral dimension of the extrinsicbase region 52 is not critical for the purposes of application of abipolar junction transistor to be formed. The patterned photoresistlayer 57 is subsequently removed, for example, by ashing. The extrinsicbase region 52 includes the extrinsic base semiconductor material, has adoping of the first conductivity type, and provides an electricalcontact to the portion of the top semiconductor portion that is incontact with the extrinsic base region 52.

Referring to FIG. 4, a dielectric spacer 70 is formed on sidewalls ofthe extrinsic base region 52 and on top surfaces of regions of the topsemiconductor portion 31 (See FIG. 3) that are proximal to the sidewallsof the extrinsic base region 52. The dielectric spacer 70 includes adielectric material such as silicon oxide, silicon nitride, siliconoxynitride, organosilicate glass, or any dielectric material that can beemployed to form a spacer as known in the art. In one embodiment, thematerial of the dielectric spacer 70 is selected to be different fromthe dielectric material of the base cap 59 so that the material of thebase cap 59 can be subsequently removed selective to the material of thedielectric spacer 70. In another embodiment, the material of thedielectric spacer 70 is selected to be different from the dielectricmaterial of the at least one shallow trench isolation structure 22 tominimize overetching into the shallow trench structure 22 when thedielectric spacer 70 is formed.

The dielectric spacer 70 can be formed, for example, by conformaldeposition of a dielectric material layer and subsequent anisotropicetch that removes the horizontal portions of the deposited dielectricmaterial layer. The conformal deposition of the dielectric materiallayer can be performed, for example, by chemical vapor deposition (CVD),atomic layer deposition (ALD), or a combination thereof. The thicknessof the dielectric spacer 70, as measured at the base that contact thetop semiconductor portion 31, can be from 10 nm to 300 nm, althoughlesser and greater thicknesses can also be employed. The dielectricspacer 70 is of unitary construction (in a single piece), and laterallycontacts the sidewalls of the extrinsic base region 52 and the base cap59. In one embodiment, the dielectric spacer 70 can include two layers,a first dielectric layer that is in contact with the sidewalls of theextrinsic base region 52 and the top surface of the regions of the topsemiconductor portion 31 that are proximal to the sidewalls of theextrinsic base region 52, and a second dielectric layer that lies on topof the first dielectric layer.

Dopants of the second conductivity type are introduced into regions ofthe top semiconductor portion 31 that are not covered by the dielectricspacer 70 and the stack of the extrinsic base region 52 and the base cap59. The second conductivity type is the opposite of the firstconductivity type. If the first conductivity type is p-type, the secondconductivity type is n-type, and vice versa. The dopants of the secondconductivity type can be introduced, for example, by ion implantationemploying the combination of the dielectric spacer 70 and the stack ofthe extrinsic base region 52 and the base cap 59 as an implantationmask. An additional implantation mask (not shown) such as a patternedphotoresist layer can also be employed if multiple devices (not shown)are present on the substrate 8.

Introduction of the dopants of the second conductivity type converts afirst region of the semiconductor portion 31 into an emitter region 34and a second region of the semiconductor portion 31 into a collectorregion 36. A remaining unimplanted region of the semiconductor portion31 constitutes a base region 32 that laterally contacts the emitterregion 34 and the collector region 36. The conversion of two regions ofthe top semiconductor portion 31 into the emitter region 34 and thecollector region 36, respectively, is performed simultaneously. Each ofthe emitter region 34 and the collector region 36 laterally contacts thebase region 32 upon formation.

The base region 32 includes a first portion of the first semiconductormaterial, has the first band gap, and has a doping of the firstconductivity type. The emitter region 34 includes a second portion ofthe first semiconductor material, has a doping of the secondconductivity type that is the opposite of the first conductivity type,and laterally contacts the base region 32. The collector region 36includes a third portion of the first semiconductor material, has adoping of the second conductivity type, laterally contacts the baseregion 32, and is spaced from the emitter region 34 by the base region32. In one embodiment, the emitter region 34 and the collector region 36can have a same dopant concentration of dopants of the secondconductivity type. The net dopant concentration of dopants of the secondconductivity type, i.e., the concentration of the dopants of the secondconductivity type less the concentration of dopants of the firstconductivity type, in the emitter region 34 and the collector region 36can be, for example, from 1.0×10¹⁷/cm³ to 3.0×10²⁰/cm³, although lesserand greater dopant concentrations can also be employed. In anotherembodiment, a masking layer (not shown) can be employed to provideasymmetric net dopant concentration of dopants of the secondconductivity type across the emitter region 34 and the collector region36.

The location of the boundary between the base region 32 and the emitterregion 34 and the location of the boundary between the base region 32and the collector region 36 is determined by the location of the outersidewall of the dielectric spacer 70, the lateral straggle of implantedions of the second conductivity type, and the subsequent diffusion ofthe implanted ions. If the ion implantation is performed along a surfacenormal of the top semiconductor portion 31, the lateral offset of theboundary between the base region 32 and the emitter region 34 from thebottommost portion of the outer sidewall of the dielectric spacer 70over the emitter region 34 can be the same as the lateral offset of theboundary between the base region 32 and the collector region 36 from thebottommost portion of the outer sidewall of the dielectric spacer 70over the collector region 36. In one embodiment, if the base cap layer59L has the same stopping power as, or a greater stopping power than,the top semiconductor portion 31 for ion implantation of dopants of thesecond conductivity type, the energy of the ion implantation can beselected such that dopants of the second conductivity type reaches thebottommost region of the top semiconductor portion 31, while notpenetrating into the extrinsic base region 52.

The bottom surface of the dielectric spacer 70 is in contact with aperipheral portion of the top surface of the emitter region 34, aperipheral portion of the top surface of the collector region 36, andtwo disjoined peripheral portions of the top surface of the base region32. In one embodiment, the entirety of the interface between the baseregion 32 and the extrinsic base region 52 can be substantially coplanarwith the entirety of the top surface of the emitter region 34 and theentirety of the top surface of the collector region 36. The buriedinsulator layer 20 has a planar top surface that contacts the baseregion 32, the emitter region 34, and the collector region 36.

Referring to FIG. 5, a second semiconductor material having a secondband gap that is greater than the first band gap is selectivelydeposited on the semiconductor surfaces of the emitter region 34 and thecollector region 36, while not growing from dielectric surfaces of theexemplary structure. The second semiconductor material can be anysemiconductor material such as the specifically listed semiconductormaterial for the first semiconductor material or any other semiconductormaterial known in the art, provided that the second band gap of thesecond semiconductor material is greater than the first band gap of thefirst semiconductor material.

The second semiconductor material is deposited employing a selectivedeposition process, in which the second semiconductor material growsfrom semiconductor surfaces and does not grow from dielectric surfaces.The second semiconductor material that grows on, and from, the emitterregion 34 constitutes an emitter contact region 64, and the secondsemiconductor material that grows on, and from, the collector region 36constitutes a collector contact region 66. In other words, the secondsemiconductor material is selectively deposited on the physicallyexposed surface of the emitter region 34 and the physically exposedsurface of the collector region 36, while the second semiconductormaterial does not grow from surfaces of the dielectric spacer 70, thebase cap 59, or the shallow trench isolation structure 22.

As the emitter contact region 64 grows with continued deposition of thesecond semiconductor material during the selective deposition process,the emitter contact region 64 comes into contact with a lower portion ofan outer sidewall of the dielectric spacer 70 and a peripheral topsurface of the shallow trench isolation structure 22. Likewise, as thecollector contact region 66 grows with continued deposition of thesecond semiconductor material during the selective deposition process,the collector contact region 66 comes into contact with a lower portionof another outer sidewall of the dielectric spacer 70 and anotherperipheral top surface of the shallow trench isolation structure 22. Thethickness of the emitter contact region 64 and the collector contactregion 66 is less than the height of the dielectric spacer 70, and canbe from 1 nm to 1,000 nm, although lesser and greater thicknesses canalso be employed.

During the selective deposition process, at least one semiconductorprecursor gas and at least one etchant gas are flowed into a processchamber to deposit the second semiconductor material on physicallyexposed semiconductor surfaces of the emitter region 34 and thecollector region 36. The at least one semiconductor precursor gas andthe at least one etchant gas can be any combination that enableselective deposition of the second semiconductor material as known inthe art. Non-limiting examples of the at least one semiconductorprecursor gas include SiH₄, SiH₂Cl₂, SiHCl₃, SiCl₄, Si₂H₆, GeH₄, Ge₂H₆,and other precursor gases for depositing the selected secondsemiconductor material. Non-limiting examples of the at least oneetchant gas include HCl.

In one embodiment, the emitter contact region 64 and the collectorcontact region 66 can be doped in-situ during the selective depositionof the second semiconductor material. Formation of the emitter contactregion 64 and the collector contact region 66 with in-situ doping can beeffected by flowing a dopant gas including a dopant atom of the secondconductivity type concurrently with, or alternately with, the at leastone semiconductor precursor gas and the at least one etchant gas. If thesecond conductivity type is n-type, the dopant gas can be, for example,PH₃, AsH₃, SbH₃, or a combination thereof. If the second conductivitytype is p-type, the dopant gas can be, for example, B₂H₆.

In another embodiment, the emitter contact region 64 and the collectorcontact region 66 can be deposited as intrinsic second semiconductormaterial portions by selective deposition of an intrinsic secondsemiconductor material, and can be subsequently doped by implantingdopants of the second conductivity type.

The emitter contact region 64 and the collector contact region 66 canhave a concentration of dopants of the second conductivity type, forexample, from 1.0×10¹⁹/cm³ to 3.0×10²¹/cm³, although lesser and greaterdopant concentrations can also be employed. In one embodiment, theconcentration of dopants of the second conductivity type in the emittercontact region 64 and the collector contact region 66 can be greaterthan the net dopant concentration of dopants of the second conductivitytype in the emitter region 34 and the collector region 36.

In one embodiment, the entirety of the base region 32, the emitterregion 34, and the collector region 36 can be single crystalline. In oneembodiment, the selective deposition of the second semiconductormaterial can be effected by performing selective epitaxy of the secondsemiconductor material. The second semiconductor material deposited inthe emitter contact region 64 can be epitaxially aligned to the firstsemiconductor material in the emitter region 34, and the secondsemiconductor material deposited in the collector contact region 66 canbe epitaxially aligned to the first semiconductor material in thecollector region 36. In other words, the emitter contact region 64 canbe epitaxially aligned to a single crystalline structure of the emitterregion 34, and the collector contact region 66 can be epitaxiallyaligned to a single crystalline structure of the collector region 36. Inthis case, the entirety of the base region 32, the emitter region 34,the collector region 36, the emitter contact region 64, and thecollector contact region 66 can be single crystalline and epitaxiallyaligned among one another.

Thus, the emitter contact region 64 including a portion of the secondsemiconductor material, having the second band gap that is greater thanthe first band gap, and having a doping of the second conductivity typeis deposited directly on the emitter region 34. The collector contactregion 66 including another portion of the second semiconductor materialis deposited directly on the collector region 36 simultaneously with thedeposition of the emitter contact region 64.

In one embodiment, the first semiconductor material can be germanium ora silicon germanium alloy having a first percentage of silicon, and thesecond semiconductor material can be silicon or a silicon germaniumalloy having a second percentage of silicon that is greater than thefirst percentage. In another embodiment, the first semiconductormaterial can be single crystalline germanium or a single crystallinesilicon germanium alloy having a first percentage of silicon, and thesecond semiconductor material can be single crystalline silicon or asingle crystalline silicon germanium alloy having a second percentage ofsilicon that is greater than the first percentage. In yet anotherembodiment, the first semiconductor material can be single crystallineor polycrystalline germanium or a single crystalline or polycrystallinesilicon germanium alloy having a first percentage of silicon, and thesecond semiconductor material can be polycrystalline silicon or apolycrystalline silicon germanium alloy having a second percentage ofsilicon that is greater than the first percentage.

In one embodiment, the dielectric spacer 70 is in contact with the baseregion 32, the emitter region 34, the emitter contact region 64, acollector region 36 that contacts the base region 32, and a collectorcontact region 66. In another embodiment, the dielectric spacer 70 is incontact with the emitter region 34, the emitter contact 64, a collectorregion 36 that contacts the base region 32, and a collector contactregion 66. This is the case in which the lateral straggle of theimplanted ions and the post-implantation diffusion of the implanted ionsresult in the emitter-base interface and the collector-base interface tobe located under the extrinsic base region 52 and not under thedielectric spacer 70. In this case, the spacer 70 does not contact thebase region 32.

Referring to FIG. 6, metal semiconductor alloy regions can be optionallyformed. In one embodiment, the dielectric cap 59 is removed selective tothe dielectric materials of the dielectric spacer 70 and the shallowtrench isolation structure 22 and the second semiconductor material ofthe emitter contact region 64 and the collector contact region 66. Forexample, if the dielectric cap 59 includes silicon nitride, and theshallow trench isolation structure 22 and the dielectric spacer 70includes silicon oxide, a wet etch employing hot phosphoric acid can beemployed to remove the dielectric cap 59 selective to the dielectricmaterials of the dielectric spacer 70 and the shallow trench isolationstructure 22 and the second semiconductor material of the emittercontact region 64 and the collector contact region 66.

The metal semiconductor alloy regions can be subsequently formed, forexample, by depositing a metal layer, inducing formation of the metalsemiconductor alloy regions during an anneal at an elevated temperature,and subsequently removing unreacted portions of the metal layerselective to the metal semiconductor alloy regions. If the secondsemiconductor material and/or the extrinsic base semiconductor materialinclude silicon and/or germanium, the various metal semiconductor alloyregions can contain a metal silicide, a metal germanide, and/or a metalgermano-silicide. The various metal semiconductor alloy regions caninclude, for example, an emitter-side metal semiconductor alloy region74, a collector-side metal semiconductor alloy region 76, and abase-side metal semiconductor alloy region 72.

Referring to FIG. 7, a contact-level dielectric material layer 90 can bedeposited and various contact via structures can be formed to provideelectrical contact to the emitter-side metal semiconductor alloy region74 (or the emitter contact region 64 if an emitter-side metalsemiconductor alloy region is not present), a collector-side metalsemiconductor alloy region 76 (or the collector contact region 66 if acollector-side metal semiconductor alloy region is not present), and abase-side metal semiconductor alloy region 72 (or the extrinsic baseregion 52 if a base-side metal semiconductor alloy region is notpresent). The contact-level dielectric material layer 90 can includeundoped silicate glass (i.e., silicon oxide), doped silicate glass,organosilicate glass, or any other dielectric material known in the artthat can be employed for forming interconnect structures. The variouscontact via structures can include an emitter-side contact via structure94, a base-side contact via structure 92, and a collector-side contactvia structure 96.

Referring to FIG. 8, a band diagram of an NPN transistor according to anembodiment of the present disclosure is shown along the direction X-X′in FIG. 7 for an exemplary case in which the first semiconductormaterial is single crystalline germanium and the second semiconductormaterial is single crystalline silicon. The material junction betweenthe n-doped germanium in the emitter region 34 and the n-doped siliconmaterial of the emitter contact region 64 is physically offset, i.e.,spaced, from the p-n junction between the n-doped germanium in theemitter region 34 and the p-doped germanium in the base region 32. Thematerial junction, which is a heterojunction, between the n-dopedgermanium in the emitter region 34 and the n-doped silicon material ofthe emitter contact region 64 provides a greater current gain than abipolar transistor that does not include a heterojunction. However,because the lattice constant of the n-doped germanium in the emitterregion 34 is matched to the lattice constant of the p-doped germanium inthe base region around the p-n junction, there is no strain around thep-n junction, and consequently, the density of dislocation is minimized.Thus, a factor that reduces current gain in conventional NPNheterojuction bipolar transistor is eliminated in the bipolar transistorstructure according to an embodiment of the present disclosure.

Referring to FIG. 9, a band diagram of a PNP transistor according to anembodiment of the present disclosure is shown along the direction X-X′for an exemplary case in which the first semiconductor material issingle crystalline germanium and the second semiconductor material issingle crystalline silicon. The material junction between the p-dopedgermanium in the emitter region 34 and the p-doped silicon material ofthe emitter contact region 64 is physically offset, i.e., spaced, fromthe p-n junction between the p-doped germanium in the emitter region 34and the n-doped germanium in the base region 32. The material junction,which is a heterojunction, between the p-doped germanium in the emitterregion 34 and the p-doped silicon material of the emitter contact region64 provides a greater current gain than a bipolar transistor that doesnot include a heterojunction. However, because the lattice constant ofthe p-doped germanium in the emitter region 34 is matched to the latticeconstant of the n-doped germanium in the base region around the p-njunction, there is no strain around the p-n junction, and consequently,the density of dislocation is minimized. Thus, a factor that reducescurrent gain in conventional PNP heterojuction bipolar transistor iseliminated in the bipolar transistor structure according to anembodiment of the present disclosure.

Referring to FIG. 10, a variation of the exemplary semiconductorstructure at a processing step corresponding to FIG. 3 is illustrated.In this variation, the top surfaces of the top semiconductor portion 31can be vertically recessed relative to the interface between theextrinsic base region 52 and an underlying region of the topsemiconductor layer 31.

Subsequently, the processing steps of FIGS. 4-6 are performed. Referringto FIG. 11, the variation of the exemplary semiconductor structure at aprocessing step corresponding to FIG. 7 is shown. The entirety of thetop surface of the emitter region 34 can be substantially coplanar witha top surface of the base region 32 in contact with the dielectricspacer 70. Likewise, the entirety of the top surface of the collectorregion 36 can be substantially coplanar with another top surface of thebase region 32 in contact with the dielectric spacer 70. Then interfacebetween the base region 32 and the extrinsic base region 52, which isthe topmost surface of the base region 32, is located above the plane ofthe top surface of the emitter region 34 and the collector region 36.

In one embodiment, a semiconductor-on-insulator (SOI) lateral bipolartransistor having an emitter region 34, a base region 32, and acollector region 36 is provided. The emitter region 34, the base region32, and the collector region 36 can be formed in the same semiconductormaterial layer including a first semiconductor material and located onthe buried insulator layer 20. The emitter region 34 is contacted by anemitter-contact region 64 including a second semiconductor material thathas a greater band gap than the first semiconductor material. Theemitter-contact region 64 is doped with the same doping type as theemitter region 34, i.e., the second conductivity type.

As long as the charge carrier diffusion length in the emitter region 34is greater than the distance between the p-n junction between the baseregion 32 and the emitter region 34 and the interface between emitterregion 34 and the emitter contact region 62, the greater band gap of theemitter contact region 64 suppresses the base current and leads to alarge current gain. The device of embodiments of the present disclosurefunctions satisfactorily for emitter regions of submicron dimensions.For example, the charge carrier diffusion length for a dopantconcentration of 10¹⁸/cm³ is on the order of 30 μm in silicon orgermanium, and the charge carrier diffusion length for a dopantconcentration of 10²⁰/cm³ is about 0.5 μm in silicon or germanium. Inone embodiment, the emitter region 34 and the collector region 36 canhave the same net dopant concentration. In this case, theemitter-collector symmetry makes such a device operate fast without anybase pushout. Such a device is suitable for operation inforward-and-reverse active modes.

While the present disclosure has been described in terms of specificembodiments, it is evident in view of the foregoing description thatnumerous alternatives, modifications and variations will be apparent tothose skilled in the art. Each of the various embodiments of the presentdisclosure can be implemented alone, or in combination with any otherembodiments of the present disclosure unless expressly disclosedotherwise or otherwise impossible as would be known to one of ordinaryskill in the art. Accordingly, the present disclosure is intended toencompass all such alternatives, modifications and variations which fallwithin the scope and spirit of the present disclosure and the followingclaims.

1. A semiconductor structure comprising a bipolar junction transistor(BJT), wherein said BJT comprises: a base region comprising a firstportion of a first semiconductor material having a first band gap andhaving a doping of a first conductivity type; an emitter regioncomprising a second portion of said first semiconductor material, havinga doping of a second conductivity type that is the opposite of saidfirst conductivity type, and laterally contacting said base region; andan emitter contact region comprising a portion of a second semiconductormaterial having a second band gap that is greater than said first bandgap, having a doping of said second conductivity type, contacting saidemitter region, and not in physical contact with said base region. 2.The semiconductor structure of claim 1, wherein said BJT furthercomprises a collector region comprising a third portion of said firstsemiconductor material, and having a doping of said second conductivitytype, laterally contacting said base region, and spaced from saidemitter region by said base region.
 3. The semiconductor structure ofclaim 2, wherein said BJT further comprises a collector contact regioncomprising another portion of said second semiconductor material, havinga doping of said second conductivity type, and contacting said collectorregion.
 4. A semiconductor structure comprising a bipolar junctiontransistor (BJT), wherein said BJT comprises: a base region comprising afirst portion of a first semiconductor material having a first band gapand having a doping of a first conductivity type; an emitter regioncomprising a second portion of said first semiconductor material, havinga doping of a second conductivity type that is the opposite of saidfirst conductivity type, and laterally contacting said base region; anemitter contact region comprising a portion of a second semiconductormaterial having a second band gap that is greater than said first bandgap, having a doping of said second conductivity type, and contactingsaid emitter region; and a collector region comprising a third portionof said first semiconductor material, and having a doping of said secondconductivity type, laterally contacting said base region, and spacedfrom said emitter region by said base region, wherein said emitterregion and said collector region have the same dopant concentration ofdopants of said second conductivity type.
 5. The semiconductor structureof claim 2, further comprising an insulator layer having a planar topsurface that contacts said base region, said emitter region, and saidcollector region.
 6. A semiconductor structure comprising a bipolarjunction transistor (BJT), wherein said BJT comprises: a base regioncomprising a first portion of a first semiconductor material having afirst band gap and having a doping of a first conductivity type; anemitter region comprising a second portion of said first semiconductormaterial, having a doping of a second conductivity type that is theopposite of said first conductivity type, and laterally contacting saidbase region; an emitter contact region comprising a portion of a secondsemiconductor material having a second band gap that is greater thansaid first band gap, having a doping of said second conductivity type,and contacting said emitter region; and an extrinsic base regioncomprising an extrinsic base semiconductor material, verticallycontacting said base region, and having a doping of said firstconductivity type.
 7. The semiconductor structure of claim 6, furthercomprising a dielectric spacer laterally contacting sidewalls of saidextrinsic base region.
 8. The semiconductor structure of claim 7,wherein said emitter contact region is in contact with an outer sidewallof said dielectric spacer.
 9. The semiconductor structure of claim 7,wherein a bottom surface of said dielectric spacer is in contact with atop surface of said emitter region and a top surface of said baseregion.
 10. The semiconductor structure of claim 9, wherein said topsurface of said emitter region and said top surface of said base regionare substantially coplanar.
 11. The semiconductor structure of claim 6,wherein an interface between said base region and said extrinsic baseregion is substantially coplanar with a top surface of said emitterregion.
 12. The semiconductor structure of claim 6, wherein an interfacebetween said base region and said extrinsic base region is located abovea plane of a top surface of said emitter region.
 13. The semiconductorstructure of claim 7, wherein said dielectric spacer is in contact withsaid base region, said emitter region, said emitter contact region, acollector region contacting said base region and comprising a thirdportion of said first semiconductor material and having a doping of saidsecond conductivity type, and a collector contact region contacting saidcollector region and comprising another portion of said secondsemiconductor material and having a doping of said second conductivitytype.
 14. The semiconductor structure of claim 1, further comprising aninsulator layer having a planar top surface that contacts said baseregion and said emitter region.
 15. The semiconductor structure of claim14, further comprising a handle substrate that contacts a planar bottomsurface of said insulator layer. 16.-25. (canceled)
 26. Thesemiconductor structure of claim 1, further comprising an emitter-sidemetal semiconductor alloy region in physical contact with said emittercontact region and not in physical contact with said emitter region. 27.The semiconductor structure of claim 1, further comprising an extrinsicbase region comprising an extrinsic base semiconductor material,vertically contacting said base region, and having a doping of saidfirst conductivity type.
 28. The semiconductor structure of claim 27,further comprising a dielectric spacer laterally contacting sidewalls ofsaid extrinsic base region.
 29. The semiconductor structure of claim 4,further comprising a collector contact region comprising another portionof said second semiconductor material, having a doping of said secondconductivity type, and contacting said collector region.
 30. Thesemiconductor structure of claim 6, wherein said emitter contact regionis not in physical contact with said base region.